DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
15
RW
0b
Read ODT Not Always Safe (sd1_cr_rdodtnas): Internal Read
ODT to CS is not always safe. Setting this bit selects the delay
(programmable) in the ODT Read Safe register field.
14
RW
0b
Write ODT Not Always Safe (sd1_cr_wrodtnas): Internal
Write ODT to CS is not always safe. Setting this bit selects the
delay (programmable) in the ODT Write Safe register field.
13:10
RW
0010b
Minimum Powerdown Exit to Non-Read command spacing
(sd1_cr_txp): This configuration register indicates the minimum
number of clocks to wait following assertion of CKE before issuing a
non-read command.
1010–1111 = Reserved.
0010–1001 = 2-9 clocks
0000–0001 = Reserved.
9:1
0
RW
000000000b
Self refresh exit count (sd1_cr_slfrfsh_exit_cnt): This
configuration register indicates the Self refresh exit count.
(Program to 255). This field corresponds to tXSNR/tXSRD in the DDR
Specification.
RW
0b
indicates only 1 DIMM populated (sd1_cr_singledimmpop):
This bit, when set, indicates that only 1 DIMM is populated.
5.2.27
C1REFRCTRL—Channel 1 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
669–66Eh
021830000C30h
RW, RO
Size:
48 bits
This register provides settings to configure the DRAM refresh controller.
Bit
Access &
Default
Description
47:42
41:37
RO
00h
Reserved
RW
10000b
Direct Rcomp Quiet Window (DIRQUIET): This configuration
setting indicates the amount of refresh_tick events to wait before the
service of rcomp request in non-default mode of independent rank
refresh.
36:32
31:27
RW
11000b
Indirect Rcomp Quiet Window (INDIRQUIET): This configuration
setting indicates the amount of refresh_tick events to wait before the
service of rcomp request in non-default mode of independent rank
refresh.
RW
00110b
Rcomp Wait (RCOMPWAIT): This configuration setting indicates the
amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
Datasheet
137
INTEL [ INTEL ]
