DRAM Controller Registers (D0:F0)
5.2.18
C1DRB2—Channel 1 DRAM Rank Boundary Address 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
604–605h
0000h
RW, RO
16 bits
Size:
The operation of this register is detailed in the description for register C0DRB0.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
RW/L
000h
Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2): See
C0DRB2 register. In Flex mode this is the topmost populated rank in
Channel 1, program this value to be cumulative of Ch0 DRB3.
5.2.19
C1DRB3—Channel 1 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
606–607h
0000h
RW, RO
16 bits
Size:
The operation of this register is detailed in the description for register C0DRB0.
Bit
Access &
Default
Description
15:10
9:0
RO
000000b
Reserved
Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See
C0DRB3 register. In Flex mode this is the topmost populated rank in
Channel 1, program this value to be cumulative of Ch0 DRB3
RW/L
000h
130
Datasheet
INTEL [ INTEL ]
