DRAM Controller Registers (D0:F0)
5.2.16
C1DRB0—Channel 1 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
600–601h
0000h
RW, RO
16 bits
Size:
The operation of this register is detailed in the description for register C0DRB0.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
RW/L
000h
Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0): See
C0DRB0 register. In Flex mode this is the topmost populated rank
in Channel 1, program this value to be cumulative of Ch0 DRB3.
5.2.17
C1DRB1—Channel 1 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
602–603h
0000h
RW, RO
16 bits
Size:
The operation of this register is detailed in the description for register C0DRB0.
Bit
Access &
Default
Description
15:1
0
RO
000000b
Reserved
9:0
RW/L
000h
Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See
C0DRB1 register. In Flex mode this is the topmost populated rank in
Channel 1, program this value to be cumulative of Ch0 DRB3.
Datasheet
129
INTEL [ INTEL ]
