DRAM Controller Registers (D0:F0)
5.2
MCHBAR
The MCHBAR registers are offset from the MCHBAR base address. Table 5-2 provides
an address map of the registers listed by address offset in ascending order. Detailed
register bit descriptions follow the table.
Table 5-2. MCHBAR Register Address Map
Address
Offset
Symbol
Register Name
Default
Value
Access
111h
CHDECMISC
C0DRB0
Channel Decode Miscellaneous
00h
RW
200–01h
Channel 0 DRAM Rank
Boundary Address 0
0000h
RO, RW
202–203h
204–205h
206–207h
208–209h
20A–20Bh
C0DRB1
C0DRB2
C0DRB3
C0DRA01
C0DRA23
Channel 0 DRAM Rank
Boundary Address 1
0000h
0000h
0000h
0000h
0000h
RW, RO
RW, RO
RW, RO
RW
Channel 0 DRAM Rank
Boundary Address 2
Channel 0 DRAM Rank
Boundary Address 3
Channel 0 DRAM Rank 0,1
Attribute
Channel 0 DRAM Rank 2,3
Attribute
RW
250–251h
252–255h
256–257h
258–25Ah
25B–25Ch
260–263h
C0CYCTRKPCHG
C0CYCTRKACT
C0CYCTRKWR
C0CYCTRKRD
C0CYCTRKREFR
C0CKECTRL
Channel 0 CYCTRK PCHG
Channel 0 CYCTRK ACT
Channel 0 CYCTRK WR
Channel 0 CYCTRK READ
Channel 0 CYCTRK REFR
Channel 0 CKE Control
0000h
00000000h
0000h
RW, RO
RW, RO
RW
000000h
0000h
RW, RO
RO, RW
00000800h
RO, RW,
RW
269–26Eh
C0REFRCTRL
Channel 0 DRAM Refresh
Control
021830000
C30h
RW, RO
29C–29Fh
600–601h
C0ODTCTRL
C1DRB0
Channel 0 ODT Control
00100000h
0000h
RO, RW
RW, RO
Channel 1 DRAM Rank
Boundary Address 0
602–603h
604–605h
606–607h
C1DRB1
C1DRB2
C1DRB3
Channel 1 DRAM Rank
Boundary Address 1
0000h
0000h
0000h
RW, RO
RW, RO
RW, RO
Channel 1 DRAM Rank
Boundary Address 2
Channel 1 DRAM Rank
Boundary Address 3
Datasheet
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INTEL [ INTEL ]
