Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 42. Input Signals (Sheet 2 of 2)
Name
Active Level
Clock
Signal Group
Qualified
LINT[1:0]
NMI
High
High
N/A
Asynch
Asynch
Asynch
—
CMOS Input
CMOS Input
Power/Other
APIC Clock
CMOS Input
CMOS Input
AGTL Input
AGTL Input
AGTL Input
Power/Other
Power/Other
CMOS Input
CMOS Input
CMOS Input
TAP Input
APIC enabled mode
APIC disabled mode
NCHCTRL
PICCLK
PREQ#
PWRGOOD
RESET#
RESET2#
RSP#
High
Low
High
Low
Low
Low
N/A
Always
Always
Always
Always
Asynch
Asynch
BCLK
BCLK
BCLK
Asynch
Asynch
Asynch
Asynch
Asynch
—
Always
RTTCTRL
SLEWCTRL
SLP#
N/A
Low
Low
Low
High
High
High
Low
High
During Stop-Grant state
SMI#
STPCLK#
TCK
TDI
TCK
TAP Input
TMS
TCK
TAP Input
TRST#
Asynch
Asynch
TAP Input
VTT_PWRGD
Power/Other
NOTE: Synchronous assertion with active TDRY# ensures synchronization.
Table 43. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
A[35:3]#
ADS#
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL Input
AGTL Input
ADS#, ADS#+1
Always
AP[1:0]#
BP[3:2]#
BPM[1:0]#
BR0#
ADS#, ADS#+1
Always
Always
Always
D[63:0]#
DBSY#
DEP[7:0]#
DRDY#
LOCK#
REQ[4:0]#
RP#
DRDY#
Always
DRDY#
Always
Always
ADS#, ADS#+1
ADS#, ADS#+1
Always
RS[2:0]#
TRDY#
Datasheet
81
INTEL [ INTEL ]
