Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 4 of 8)
Name
Type
Description
The DYN_OE allows the BSEL and VID signals to be driven out from the processor.
When this signal is low (a condition that will occur if the processor is installed in a
non-supported platform), the VID and BSEL signals will be tri-stated and the
platform pull-up resistors will set the VID and BSEL to all 1s which is a safe setting.
This signal must be connected to a 1 kΩ resistor to VTT. Refer to the platform
design guide for implementation detail and resistor tolerance.
DYN_OE
I
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
FERR#
O
When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
FLUSH#
I
On the active-to-inactive transition of RESET#, each processor samples FLUSH#
to determine its power-on configuration. See the P6 Family of Processors
Hardware Developer’s Manual for details.
This signal must be connected to a 150 Ω resistor to VCCCMOS1.5. Refer to the
platform design guide for implementation detail and resistor tolerance.
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
HIT#
I/O
I/O
HITM#
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The
processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.
IERR#
O
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE#
I
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle
snoop requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor system bus agents.
INIT#
KEY
I
I
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
Can be used to prevent legacy processors from booting in incompatible platforms.
Legacy processors use this pin as a RESET and should be tied to ground for a 0.13
micron process processor only platform but for flexible platform implementations
this pin should be a No Connect. Please refer to the appropriate Platform Design
Guide for implementation details.
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