Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 2 of 8)
Name
Type
Description
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents, and must connect the appropriate pins of all such agents, if used. However,
the processor does not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
BERR#
I/O
•
•
•
Enabled or disabled.
Asserted optionally for internal errors along with IERR#.
Asserted optionally by the request initiator of a bus transaction after it observes
an error.
•
Asserted by any bus agent when it observes an error in a bus transaction.
The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for bus arbitration to the state after
Reset, and internal count information is lost. The L1 and L2 caches are not
affected.
BINIT#
I/O
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system
bus agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BNR#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BP[3:2]#
I/O
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPM[1:0]#
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BPRI#
BR0#
I
The BR0# (Bus Request) pins drive the BREQ[0]# signal in the system. During
power-up configuration, the central agent asserts the BR0# bus signal in the
system to assign the symmetric agent ID to the processor. The processor samples
its BR0# pin on the active-to-inactive transition of the RESET# to obtain its
symmetric agent ID. The processor asserts the BR0# pin to request the system
bus. BR0# must be connected to a 10-56Ω resistor to VSS. Refer to the platform
design guide for implementation detail and resistor tolerance.
I/O
74
Datasheet
INTEL [ INTEL ]
