Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 5 of 8)
Name
Type
Description
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of
all APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Intel Pentium processor. Both signals are asynchronous.
LINT[1:0]
I
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of
the first transaction end of the last transaction.
LOCK#
I/O
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
The NCHCTRL input signal provides AGTL pull-down strength control. The
processor samples this input to determine the N-channel device strength for pull-
down when it is the driving agent. This signal must be connected to a 14ohm
resistor to VTT. Refer to the platform design guide for implementation detail and
resistor tolerance.
NCHCTRL
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICCLK
I
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PICD[1:0]
I/O
The processor has an internal analog PLL clock generator that requires a quiet
power supply. PLL1 and PLL2 are inputs to this PLL and must be connected to
VCCCORE through a low pass filter that minimizes jitter. See the platform design
guide for implementation details.
PLL1, PLL2
I
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PRDY#
PREQ#
O
I
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (VCC
,
etc.) are stable and within their specifications. Clean implies that the signalCwOiRllE
remain low (capable of sinking leakage current), without glitches, from the time that
the power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width
specification in Table 18, and be followed by a 1 ms RESET# pulse.
PWRGOOD
I
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
REQ[4:0]#
I/O
Datasheet
77
INTEL [ INTEL ]
