Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 7 of 8)
Name
Type
Description
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
SMI#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power state. The processor stops providing internal clock signals to all
processor core units except the bus and APIC units. The processor continues to
snoop bus transactions and latch interrupts. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts, and
resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
STPCLK#
I
The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TCK
I
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDI
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TDO
O
O
I
Thermal Diode Cathode. This signal is used to calculate core (junction)
temperature. See Section 4.1.
THERMDN
THERMDP
Thermal Diode Anode. This signal is used to calculate core (junction) temperature.
See Section 4.1.
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active or core power is
removed. There is no hysteresis built into the thermal sensor itself; as long as the
die temperature drops below the trip level, a RESET# pulse will reset the processor
and execution will continue. If the temperature has not dropped below the trip level,
the processor will continue to drive THERMTRIP# and remain stopped.
THERMTRIP#
O
In the event the processor drives the THERMTRIP# signal active during valid
operation, both the VCC and VTT supplies to the processor must be turned off to
prevent thermal runaway of the processor. Valid operation refers to the operating
conditions where the THERMTRIP# signal is guaranteed valid. The time required
from THERMTRIP# asserted to VCC rail at 1/2 nominal is 5 seconds and
THERMTRIP# asserted to VTT rail at 1/2 nominal is 5 seconds. Once Vcc and VTT
supplies are turned off the THERMTRIP# signal will be deactivated. System logic
should ensure no “unsafe” power cycling occurs due to this deassertion.
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TMS
I
I/O
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRDY#
TRST#
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
The VCMOS_REF input pin supplies non-AGTL reference voltage, which is typically
2/3 of VCMOS. VCMOS_REF is used by the non-AGTL receivers to determine if a
signal is a logical 0 or a logical 1.
VCMOS_REF
I
The Thevenin equivalent impedance of the VCMOS_REF generation circuits must be
less than 0.5 kΩ/1 kΩ (i.e., top resistor 500 Ω, bottom resistor 1 kΩ).
Datasheet
79
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