Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 6 of 8)
Name
Type
Description
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCCCORE and
CLK have reached their proper specifications. On observing active RESET#, all
processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Developer’s Manual for details.
RESET#
I
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the power on Reset vector
(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all
processor system bus agents.
RESET# is the only AGTL signal which does not have on-die termination.
Therefore, it is necessary to place a discrete 56Ω resistor to VTT. Refer to the
platform design guide for implementation detail and resistor tolerance.
RESET2# pin is provided to differentiate the processor from the previous
generation Intel Celeron processor. The 0.13 micron process based processor
does not use the RESET2# pin. Refer to the platform design guide for the proper
connections of this signal.
RESET2#
I
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
RP#
I/O
I/O
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RS[2:0]#
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
RSP#
I
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
The RTTCTRL input signal provides AGTL termination control. The processor
samples this input to set the termination resistance value for the on-die AGTL
termination. This signal must be connected to a 56 Ω resistor to VSS on a uni-
processor platform or a 68 Ω resistor to VSS on a dual-processor platform. Refer to
the platform design guide for implementation detail and resistor tolerance.
RTTCTRL
I
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The SLEWCTRL input signal provides AGTL slew rate control. The processor
samples this input to determine the slew rate for AGTL signals when it is the driving
agent. This signal must be connected to a 110 Ω resistor to VSS. Refer to the
platform design guide for implementation detail and resistor tolerance.
SLEWCTRL
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SLP#
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Datasheet
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