Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 3 of 8)
Name
Type
Description
The BSEL signals are CMOS signals which are used to select the system bus
frequency. A BSEL[1:0] = ‘01’ selects a 100 MHz system bus frequency. The
frequency is determined by the processor(s), chipset, and frequency synthesizer
capabilities. All system bus agents must operate at the same frequency. The
processor operates at 100 MHz system bus frequency.
BSEL[1:0]
O
These signals must be pulled up to 3.3V power rail with 330 Ω – 1 KΩ resistors and
provided as a frequency selection signal to the clock driver/synthesizer and chipset.
Refer to the platform design guide for implementation detail and resistor tolerance.
In Single-ended clock mode the CLKREF input is a filtered 1.25V supply voltage for
the processor PLL. A voltage divider and decoupling solution is provided by the
motherboard. See the design guide for implementation details.
CLKREF
I
When the processor operates in differential clock mode, this signal becomes
BCLK#.
The CPUPRES# signal is defined to allow a system design to detect the presence
of a processor in a PGA370 socket. Combined with the VID combination of
VID[25mV,3:0]= 11111 (see Section 2.6), a system can determine if a socket is
occupied, and whether a processor core is present. See the table below for states
and values for determining the presence of a device.
PGA370 Socket Occupation Truth Table
CPUPRES#
O
Signal
Value
Status
0
CPUPRES#
VID[25mV,3:0]
Processor core installed in the PGA370
socket.
Anything other
than ‘11111’
CPUPRES#
VID[25mV,3:0] Any value
1
PGA370 socket not occupied.
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
D[63:0]#
DBSY#
I/O
I/O
I
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEFER#
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DEP[7:0]#
I/O
A tri-state (high-impedance) output. Can be used for platforms that need to
differentiate the previous generation Intel Celeron processors for the PGA370
socket that support VTT = 1.50 V from the new processors (AF36=VSS) that
support VTT = 1.25 V . The output on this signal is stable when VTT is stable. Refer
to the appropriate Platform Design Guide for implementation details.
DETECT
DRDY#
O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
I/O
Datasheet
75
INTEL [ INTEL ]
