Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 40. Signal Description (Sheet 8 of 8)
Name
Type
Description
The VID[3:0, 25 mV] (Voltage ID) pins can be used to support automatic selection
of power supply voltages. These pins are CMOS signals that must be pulled up to
3.3 V power rail with 1 KΩ resistors. The VID pins are needed to cleanly support
voltage specification variations on processors. See Table 3 for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
VID [3:0,25mV]
O
The VREF input pins supply the AGTL reference voltage, which is typically 2/3 of
VTT. VREF is used by the AGTL receivers to determine if a signal is a logical 0 or a
logical 1.
VREF
I
I
The VTT_PWRGD signal informs the system that the VID/BSEL signals are in their
correct logic state. During Power-up, the VID signals will be in an indeterminate
state for a small period of time. The voltage regulator or the VRM should not sample
and/or latch the VID signals until the VTT_PWRGD signal is asserted. The
assertion of the VTT_PWRGD signal indicates the VID signals are stable and are
driven to the final state by the processor. Refer to Figure 6 for power-up timing
sequence for the VTT_PWRGD and the VID signals
VTT_PWRGD
7.2
Signal Summaries
Table 41 through Table 44 list attributes of the processor output, input, and I/O signals.
Table 41. Output Signals
Name
Active Level
Clock
Signal Group
BSEL[1:0]
CPUPRES#
DETECT
High
Low
High
Low
Low
Low
High
Low
N/A
Asynch
Asynch
Asynch
Asynch
Asynch
BCLK
Power/Other
Power/Other
Power/Other
CMOS Output
CMOS Output
AGTL Output
TAP Output
FERR#
IERR#
PRDY#
TDO
TCK
THERMTRIP#
VID[3:0, 25mV]
Asynch
Asynch
CMOS Output
Power/Other
Table 42. Input Signals (Sheet 1 of 2)
Name
Active Level
Clock
Signal Group
Qualified
A20M#
BCLK
Low
High
Low
Low
Low
Low
Low
High
N/A
Asynch
—
CMOS Input
System Bus Clock
AGTL Input
Always1
Always
BPRI#
DEFER#
FLUSH#
IGNNE#
INIT#
BCLK
Always
BCLK
AGTL Input
Always
Asynch
Asynch
Asynch
Asynch
Asynch
CMOS Input
CMOS Input
CMOS Input
CMOS Input
Power/Other
Always1
Always1
Always1
INTR
APIC disabled mode
KEY
80
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