Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Figure 10. BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform
Tp
Th
Vih diff
Vringback
(rise)
V2
V3
V1
0V
Vringback
(fall)
Vil diff
Tr
Tf
Th
Tl
=
=
=
=
=
T5, T25, T34, (Rise Time)
T6, T26, T35, (Fall Time)
T3, T23, T32, (High Time)
T4, T24, T33, (Low Time)
Tf
Tl
Tr
Tp
T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK is referenced to 0.30V (Differential Mode), 0.50V (Single-Ended Mode)
TCK is referenced to Vref - 200 mV, PICCLK is referenced to 0.4V.
V2 = BCLK is refernced to 0.9V (Differental Mode), 2.0V (Single-Ended Mode)
TCK is referenced to Vref + 200 mV, PICCLK is refernced to 1.6V
V3 = BCLK and BLCK# crossing point of the rising edge of BLCK and the falling edge of BCLK# (Differential Mode),
BCLK i refereced to 1.25V (Single-Ended Mode), PICCLK is reference to 1.0V, TCK is referenced to Vcmosref
Figure 11. System Bus Valid Delay Timings
BCLK#
BCLK
Tx
Tx
Valid
Valid
V
Signal
Tpw
Tx = T7, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
V = Vref for AGTL signal group; Vcmosref for CMOS, APIC and TAP signal groups
Datasheet
37
INTEL [ INTEL ]
