Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
4. All CMOS outputs shall be asserted for at least 2 system bus clocks.
5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK and BCLK# are stable.
Table 19. System Bus Timing Specifications (Reset Conditions) 1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time
Before deassertion
of RESET#
4
BCLKs
13
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time
After clock that
deasserts RESET#
2
20
BCLKs
13
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all the processor up to 1.40 GHz frequency.
Table 20. System Bus Timing Specifications (APIC Clock and APIC I/O)1, 2, 3
T# Parameter
T21: PICCLK Frequency
Min
Max
Unit
Figure
Notes
2.0
30.0
10.5
10.5
0.25
0.25
8.0
33.3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
T22: PICCLK Period
500.0
10
10
10
10
10
12
12
11
10
T23: PICCLK High Time
@ > 1.60 V
@ < 0.40 V
(0.40 V – 1.60 V)
(1.60 – 0.40 V)
4
T24: PICCLK Low Time
T25: PICCLK Rise Time
3.0
3.0
T26: PICCLK Fall Time
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
2.5
4
1.5
8.7
4, 5, 6
1.5
12.0
4, 5, 6
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. These specifications are tested during manufacturing.
3. All timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.9 V at the processor pins.
All APIC I/O signal timings are referenced at 1.0 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
34
Datasheet
INTEL [ INTEL ]
