Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 21. System Bus Timing Specifications (TAP Connection)
1,2,3
T# Parameter
T30: TCK Frequency
Min
Max
Unit
Figure
Notes
16.667
MHz
ns
T31: TCK Period
60.0
25.0
25.0
10
10
10
T32: TCK High Time
T33: TCK Low Time
ns
Vcmos_ref + 0.200 V, 10
Vcmos_ref – 0.200 V, 10
ns
(Vcmos_ref – 0.200 V) –
(Vcmos_ref + 0.200 V),
T34: TCK Rise Time
T35: TCK Fall Time
5.0
5.0
ns
ns
10
10
4, 10
(Vcmos_ref + 0.200 V) –
(Vcmos_ref – 0.200 V),
4, 10
T36: TRST# Pulse Width
40.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
16
16
16
16
16
16
16
16
Asynchronous, 10
T37: TDI, TMS Setup Time
T38: TDI, TMS Hold Time
5
14.0
1.0
5
T39: TDO Valid Delay
10.0
25.0
25.0
25.0
6, 7
T40: TDO Float Delay
6, 7, 10
6, 8, 9
6, 8, 9, 10
5, 8, 9
5, 8, 9
T41: All Non-Test Outputs Valid Delay
T42: All Non-Test Inputs Setup Time
T43: All Non-Test Inputs Setup Time
T44: All Non-Test Inputs Hold Time
2.0
5.0
13.0
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. All timings for the TAP signals are referenced to the TCK rising edge at 1.0 V at the processor pins. All TAP
signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Datasheet
35
INTEL [ INTEL ]
