Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Figure 12. System Bus Setup and Hold Timings
BCLK#
VCross
BCLK
Th
Ts
V
Valid
VCross
= Crossing point of BLCK and BCLK#
Ts = T8, T27 (Setup Time)
Th = T9, T28 (Hold Time)
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups
Figure 13. System Bus Reset and Configuration Timings
BCLK#
BCLK
T8
T9
RESET#
T10
T17
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T16
Valid
T9 = (AGTL+ Input Hold Time)
T8 = (AGTL+ Input Setup Time)
T10 = (RESET# Pulse Width)
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
T16 = (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T17 = (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
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Datasheet
INTEL [ INTEL ]
