Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in Table 23, Table 24, and Table 27 ensures that
signal quality effects will not adversely affect processor operation.
3.1
BCLK/BCLK# & PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 24 describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK/BCLK#) and APIC clock (PICCLK) signals. References made to BCLK signal
quality specifications also applies to BCLK#. Figure 18 describes the signal quality waveform for
the system bus clock at the processor pins.
Table 23. BCLK (Single-Ended Clock Mode) Signal Quality Specifications for Simulation at
the Processor Pins
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK VIL
V2: BCLK VIH
0.3
V
V
V
V
V
18
18
18
18
18
2.2
-0.5
2.0
V3: BCLK Absolute Voltage Range
V4: BCLK Rising Edge Ringback
V5: BCLK Falling Edge Ringback
3.1
0.5
2
2
Table 24. BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality Specifications
for Simulation at the Processor Pins
1
T# Parameter
V1: BCLK VIL
Min
Nom
Max
Unit
Figure
Notes
-0.2
0.35
0.40
1.45
V
V
V
V
V
V
V
V
V
V
18
18
18
18
18
18
18
18
18
18
V1: PICCLK VIL
V2: BCLK VIH
0.92
1.60
-0.2
-0.4
0.35
1.60
V2 PICCLK VIH
V3: BCLK Absolute Voltage Range
V3: PICCLK Absolute Voltage Range
V4: BCLK Rising Edge Ringback
V4: PICCLK Rising Edge Ringback
V5: BCLK Falling Edge Ringback
V5: PICCLK Falling Edge Ringback
1.45
2.4
2
2
2
2
-0.35
0.40
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/BCLK# and PICCLK signals can dip back to after passing the VIH (rising) or VIL (falling)
voltage limits. This specification is an absolute value.
Datasheet
41
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