Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 16. Valid System Bus to Core Frequency Ratios 1, 2, 3
BCLK Frequency
(MHz)
Frequency
Multiplier
Processor
Core Frequency
1.4 GHz
1.30
1.20
1.204
1.1A
1A
1.40
100
100
100
100
100
100
100
14
13
12
12
11
10
9
1.30 GHz
1.20 GHz
1.204 GHz
1.1A GHz
1A GHz
900
900 MHz
NOTES:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the
processor.
3. Individual processors will only operate at their specified system bus frequency; 100 MHz.
4. 1.20 GHz at VccCORE = 1.475 volts and S-Spec number SL5XS.
Table 17. System Bus Timing Specifications (AGTL Signal Group)
1,2,3
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL Output Valid Delay
T8: AGTL Input Setup Time
T9: AGTL Input Hold Time
T10: RESET# Pulse Width
0.40
1.30
1.00
1.00
3.25
ns
ns
ns
ms
11
12
12
13
4
5, 6, 7, 10
8
6, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz on 0.13 micron
process.
2. These specifications are tested during manufacturing.
3. All timings for the AGTL signals are referenced to the rising edge of BCLK and the falling edge of BCLK# at
the processor pin. All AGTL signal timings (compatibility signals, etc.) are referenced at 0.80 V at the
processor pins.
4. Valid delay timings for these signals are specified into 50 Ω to 1.25 V, VREF at 0.8 V ±2% and with 56 Ω or
68 Ω on-die RTT
.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from VREF – 200 mV to VREF + 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 0.8 V swing from VTT – 0.8V to VTT. This assumes an edge rate of 3 V/ns.
9. This should be measured after VCCCORE, VTT, VccCMOS, and BCLK (and BCLK#) are stable
10.BREQ signals observe a 1.2 ns minimum setup time.
Table 18. System Bus Timing Specifications (CMOS Signal Group)
,2,3,4
T# Parameter
Min
Max
Unit
Figure
Notes 1
T14: CMOS Input Pulse Width, except
PWRGOOD
Active and
Inactive states
2
BCLKs
BCLKs
11
15
T15: PWRGOOD Inactive Pulse Width
10
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
Datasheet
33
INTEL [ INTEL ]
