Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 22. Platform Power-On Timings
2
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Valid Time Before VTT_PWRGD
T46: Valid Time Before PWRGOOD
T47: RESET# Inactive to Valid Outputs
T48: RESET# Inactive to Drive Signals
1.0
2.0
1
mS
mS
14
14
14
14
1
1
1
1
BCLK
BCLK
4
NOTES:
1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform
during processor power-up sequence.
2. Configuration Input signals include: A[14:5], BR0#, INIT#. For timing of these signals, refer to Table 18 and
Figure 13.
Notes: For Figure 9 through Figure 19, the following apply:
1. Figure 9 through Figure 19 are to be used in conjunction with Table 14 through Table 21.
2. All timings for the AGTL signals at the processor pins are referenced to the rising edge of
BCLK and the falling edge of BCLK# at the crossing point for differential clock mode and to
the rising edge of BCLK at BCLKVREF (1.25 V) for single-ended clock mode. All AGTL
signal timings (address bus, data bus, etc.) are referenced at 2/3VTT at the processor pins.
3. All timings for the APIC I/O signals at the processor pins are referenced to the PICCLK rising
edge at 0.9 V. All APIC I/O signal timings are referenced at 1.0 V at the processor pins.
4. All timings for the TAP signals at the processor pins are referenced to the TCK rising edge at
1.0 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.
Figure 9. Clock Waveform
V ih
B C L K
V cro ss
B C L K #
V il
T p
T p = T 1 (B C LK P eriod)
N O T E : S ingle-E nded clock uses B C LK on ly,
D ifferential clock uses B LC K and B C LK #
36
Datasheet
INTEL [ INTEL ]
