Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Figure 14. Platform Power-On Sequence and Timings
Vtt, Vref
Vcmosref
VID
Valid
Valid
BSEL[1:0]
VTT_PWRGD
VCC_Core
T45
BCLK#
BCLK
PICCLK
T46
VCC_PWRGD
Configuration Inputs
RESET#
Inactive
Valid Config
T47
Active
Valid
Valid
Valid
Valid
THERMTRIP#
PICD[1:0]
AGTL Outputs
All other CMOS
Outputs
Inactive
Active
T48
All other Inputs
Figure 15. Power-On Reset and Configuration Timings
BCLK
VccCORE, VTT
,
VREF
VIH, min
Tb
PWRGOOD
VIL, max
Ta
RESET#
TC
Configuration
(A20M#, IGNNE#,
INTR, NMI)
Valid Ratio
Ta = T15 (PWRGOOD Inactive Pulse)
Tb = T10 (RESET# Pulse Width)
Tc = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Datasheet
39
INTEL [ INTEL ]
