Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
2.13
System Bus Timing Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 14 through Table 21 list the timing specifications associated with the processor system bus.
These specifications are broken into the following categories: Table 14 contains the system bus
clock specifications for Single-ended clock mode operation and Table 15 contains the system bus
clock specifications for Differential clock mode operation. Table 17 contains the AGTL
specifications, Table 18 contains the CMOS signal group specifications, Table 19 contains timings
for the reset conditions, Table 20 and covers APIC bus timing, and Table 21 covers TAP timing.
All processor system bus timing specifications for the AGTL signal group are relative to the rising
edge of the BCLK input. All AGTL timings are referenced to VREF for both ‘0’ and ‘1’ logic levels
unless otherwise specified..
AGTL layout guidelines are also available in the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
7
Table 14. System Bus Timing Specifications (Single-Ended Clock)
100 MHz
1,4
T# Parameter
Unit
Figure
Notes
Min
Max
T1: BCLK Period - average
10.0
10.15
nS
nS
9
2
2
T1abs: BCLK Period - Instantaneous
minimum
9.75
T2: BCLK Period Stability
T5: BCLK Rise Time
T6: BCLK Fall Time
T3: BCLK High Time
T4: BCLK Low Time
T7: BCLK Input High
T8: BCLK Input Low
250
1.6
1.6
pS
nS
nS
nS
nS
V
2
3
3
5
6
0.4
0.4
2.5
2.4
2.2
10
10
10
10
0.3
V
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency on
0.13 micron process.
2. Period, jitter, offset and skew measured at 1.25 V.
3. Measured from 0.5 to 2.0 V.
4. CLKREF (BCLK#) = 1.25 V with ±5% DC tolerance. CLKREF must be generated from a stable source. AC
tolerances must be less than -40 dB at 1 MHz.
5. BCLK High Time is measured above 2.0 V.
6. BCLK Low Time is measured below 0.5 V.
Datasheet
31
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