E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
4.2.7
PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table
specifies this and other similar information.
Table 12. Primary Vendor-Specific Extended Query
Offset(1)
Length
(bytes)
Description
Intel
StrataFlash™
Memory
(P)h
03h
Primary extended Query table unique ASCII string “PRI”
31:
32:
33:
0050h
0052h
0049h
(P +3)h
(P +4)h
(P +5)h
01h
01h
04h
Major version number, ASCII
34:
35:
0031
0031
Minor version number, ASCII
Optional Feature and Command Support
36:
37:
38:
39:
000Ah
0000h
0000h
0000h
bit 0
bit 1
bit 2
bit 3
bit 4
Chip Erase Supported
Suspend Erase Supported
Suspend Program Supported (1=yes, 0=no)
Lock/Unlock Supported
Queued Erase Supported
(1=yes, 0=no)
(1=yes, 0=no)
(1=yes, 0=no)
(1=yes, 0=no)
bits 5–31 Reserved for future use; undefined bits
are “0”
(P +9)h
01h
Supported functions after Suspend
3A:
0001h
Read Array, Status, and Query are always supported
during suspended Erase. This field defines other
operations supported.
bit 0
Program supported after Erase Suspend
(1=yes, 0=no)
bits 1–7 Reserved for future use; undefined bits
are “0”
(P +A)h
02h
Block Status Register Mask
3B:
3C:
0001h
0000h
Defines which bits in the Block Status Register section of
Query are implemented.
bit 0
bit 1
Block Status Register Lock Bit [BSR.0] active
(1=yes, 0=no)
Block Status Register Valid Bit [BSR.1] active
(1=yes, 0=no)
bits 2–15 Reserved for future use; undefined bits
are “0”
NOTE:
1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software
should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.
25
ADVANCE INFORMATION
INTEL [ INTEL ]
