INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
4.2.6 DEVICE GEOMETRY DEFINITION
This field provides critical details of the flash device geometry.
E
Table 11. Device Geometry Definition
Description
Offset
Length
(bytes)
Intel
StrataFlash™
Memory
27h
01h
Device Size = 2N in number of bytes.
27:
27:
0017h
(64-Mbit)
0016h
(32-Mbit)
28h
02h
Flash Device Interface description
28:
29:
0002h
0000h
value
meaning
0000h
0002h
x8 asynchronous
x8/x16 asynchronous
2Ah
2Ch
02h
01h
Maximum number of bytes in write buffer = 2N
2A:
2B:
0005h
0000h
Number of Erase Block Regions within device:
bits 7–0 = x = # of Erase Block Regions
Erase Block Region Information
2C:
0001h
2Dh
04h
y: 64 Blocks
(64-Mbit)
2D:
2E:
bits 15–0 = y, where y+1 = Number of Erase Blocks
of identical size within region
003Fh
0000h
bits 31–16 = z, where the Erase Block(s) within this
Region are (z) times 256 bytes
y: 32 Blocks
(32-Mbit)
2D:
2E:
001Fh
0000h
z: (128 KB size)
2F:
30:
0000h
0002h
24
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