E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
4.2.5
SYSTEM INTERFACE INFORMATION
The following device information can optimize system interface software.
Table 10. System Interface Information
Offset
Length
(bytes)
Description
Intel
StrataFlash™
Memory
1Bh
01h
01h
01h
01h
VCC Logic Supply Minimum
Program/Erase voltage
1B:
0045h
0055h
0000h
0000h
bits 7–4
bits 3–0
BCD volts
BCD 100 mv
1Ch
1Dh
1Eh
VCC Logic Supply Maximum
Program/Erase voltage
1C:
1D:
1E:
bits 7–4
bits 3–0
BCD volts
BCD 100 mv
VPP [Programming] Supply
Minimum Program/Erase voltage
bits 7–4
bits 3–0
HEX volts
BCD 100 mv
VPP [Programming] Supply
Maximum Program/Erase voltage
bits 7–4
bits 3–0
HEX volts
BCD 100 mv
1Fh
20h
21h
22h
23h
24h
25h
26h
01h
01h
01h
01h
01h
01h
01h
01h
Typical time-out per single byte/word
program, 2N µs
1F:
20:
21:
22:
23:
24:
25:
26:
0007h
0007h
000Ah
0000h
0004h
0004h
0004h
0000h
Typical time-out for max. buffer write,
2N µs
Typical time-out per individual block
erase, 2N ms
Typical time-out for full chip erase,
2N ms (0000h = not supported)
Maximum time-out for byte/word program,
2N times typical
Maximum time-out for buffer write,
2N times typical
Maximum time-out per individual
block erase, 2N times typical
Maximum time-out for chip erase,
2N times typical (00h = not supported)
23
ADVANCE INFORMATION
INTEL [ INTEL ]
