INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
Table 4. Intel StrataFlash™ Memory Command Set Definitions(14)
Command
Scaleable Bus Notes
or Basic Cycles
Command Req'd.
Set(15)
First Bus Cycle
Second Bus Cycle
Oper(1) Addr(2) Data(3,4) Oper(1) Addr(2) Data(3,4)
Read Array
SCS/BCS
SCS/BCS
1
Write
Write
X
X
FFH
90H
Read Identifier
Codes
≥2
5
6
Read
IA
ID
Read Query
SCS
≥ 2
Write
Write
X
X
98H
70H
Read
Read
QA
X
QD
Read Status
Register
SCS/BCS
2
SRD
Clear Status
Register
SCS/BCS
1
Write
X
50H
E8H
Write to Buffer
SCS/BCS
SCS/BCS
> 2
2
7,8,9
Write
Write
BA
X
Write
Write
BA
PA
N
Word/Byte
Program
10,11
40H
or
PD
10H
Block Erase
SCS/BCS
SCS/BCS
2
1
9,10
9,10
Write
Write
X
X
20H
B0H
Write
BA
D0H
Block Erase
Suspend
Block Erase
Resume
SCS/BCS
1
10
Write
X
D0H
Configuration
SCS
SCS
SCS
2
2
2
Write
Write
Write
X
X
X
B8H
60H
60H
Write
Write
Write
X
BA
X
CC
01H
D0H
Set Block Lock-Bit
12
13
Clear Block Lock-
Bits
Set Master Lock-
Bit
2
12,13
Write
X
60H
Write
X
F1H
16
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