Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 14. Power Down Sequencing and Timings (V
Leading)
CCT
VCCT-12%
VCCT, VREF
VCMOS,
CMOSREF,
CLKREF
Ta
VTTPWRGD
VILVTTPWR
VID[4:0]
Valid
BSEL[1:0]
VCC
Tb, Tc, Td
BCLK/BCLK#
Valid
PICCLK
Valid
PWRGOOD
RESET#
PICD[1:0]
Valid
Valid
Valid
AGTL OUTPUTS
OTHER CMOS OUTPUTS
ALL INPUTS
V0045-00
NOTES:
1. Ta = T20A (Time from VCCT-12% to VTTPWRGD low)
2. Tb = T20B (All outputs valid after VTTPWRGD low)
3. Tc = T20C (All inputs required valid after VTTPWRGD low)
4. Td = T20D (VID, BSEL signals valid after VTTPWRGD low)
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Datasheet