Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 8. BCLK/BCLK# Waveform (Differential Mode)
T1
VIH_DIFF
V4
0V
V5
VIl_DIFF
T5
T6
Figure 9. Valid Delay Timings
Vc
Vc
CLK
TX
T
x
V
Valid
Valid
Signal
TPW
D0004-00
NOTES:
1. Tx = T7, T11, T29 (Valid Delay)
2. Tpw = T14, T14B (Pulse Width)
3. V = VREF for AGTL signal group; 1.0V for CMOS, Open-drain, APIC, and TAP signal groups
4. Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)
= 1.25V (Single Ended Clock)
Figure 10. Setup and Hold Timings
Vc
CLK
Th
Ts
V
Valid
Signal
D0005-00
NOTES:
1. Ts = T8, T27 (Setup Time)
2. Th =T9, T28 (Hold Time)
3. V = VREF for AGTL signals; 1.0 V for CMOS, APIC, and TAP signals
4. Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)
= 1.25 V (Single Ended Clock)
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Datasheet
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