Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 12. Power-on Sequence and Reset Timings
BCLK/BCLK#
VCCT
T
d
VIHVTTPWR,min
VTTPWRGD
VILVTTPWR,max
T
e
VID[4:0]/
BSEL[1:0]
Valid
CMOSREF/
CLKREF/VREF
VCC
T
a
T
c
VIH18,min
PWRGOOD
VIL18,max
T
b
RESET#
V0040-00
NOTES:
1. Ta = T15 (PWRGOOD Inactive Pulse Width)
2. Tb = T18 (RESET#/PWRGOOD Setup Time)
3. Tc = T18B (Setup time from VCC valid until PWRGOOD assertion)
4. Td = T18A (Setup time from VCCT valid to VTTPWRGD assertion)
5. Te = T18C(VID, BSEL valid time before VTTPWRGD assertion)
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Datasheet