Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
4.0
System Signal Simulations
Systems must be simulated using IBIS models to determine if they are compliant with this
specification. All references to BCLK signal quality also apply to BCLK# for Differential
Clocking.
4.1
System Bus Clock (BCLK) and PICCLK DC
Specifications and AC Signal Quality Specifications
Table 30. BCLK (Differential) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit Figure
Notes
V1
V2
VIL,BCLK
VIH,BCLK
-0.2
0.35
1.45
V
V
1
1
0.92
Undershoot/
Overshoot, 2
V3
VIN Absolute Voltage Range
-0.2
1.45
V
V4
V5
BCLK Rising Edge Ringback
BCLK Falling Edge Ringback
0.35
V
V
6
6
3
3
-0.35
1.45
BCLK Voltage in Deep Sleep
State
VBCLK_DPSLP
0.4
0
V
V
4
4
VBCLK_DPSLP
- 0.2 V
BCLK# Voltage in Deep Sleep
State
VBCLK#_DPSLP
NOTES:
1. The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK.
2. These specifications apply only when BCLK, BCLK# are running.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage
the differential waveform may go to after passing the VIH_DIFF (rising) or VIL_DIFF (falling) levels.
VIL_DIFF (max) = -0.57 V, VIH_DIFF (min) = 0.57 V.
4. Applies when BCLK and BCLK# are stopped in Deep Sleep State.
Table 31. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min Max Unit
Figure
Notes
V1
V2
VIL,BCLK
VIH,BCLK
IN Absolute Voltage Range
0.3
V
V
V
V
V
18
18
18
18
18
1
2.2
1
V3
V
-0.5 3.1
2.0
Undershoot/Overshoot, 2
Absolute Value, 3
Absolute Value, 3
V4
BCLK Rising Edge Ringback
BCLK Falling Edge Ringback
V5
0.5
NOTES:
1. The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK. BCLK must be stopped in the low
state.
2. These specifications apply only when BCLK is running. BCLK may not be above VIH,BCLK,max or below
V
BCLK,min for more than 50% of the clock cycle.
IL,
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may go to after passing the VIH,BCLK (rising) or VIL,BCLK (falling) voltage limits.
Datasheet
47
INTEL [ INTEL ]
