Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 15. Test Timings (Boundary Scan)
TCK
T
T
w
v
0.75V
TDI, TMS
T
T
s
r
Input
Signals
T
T
u
x
TDO
T
T
z
y
Output
Signals
D0008-01
NOTES:
1. Tr = T43 (All Non-Test Inputs Setup Time)
2. Ts = T44 (All Non-Test Inputs Hold Time)
3. Tu = T40 (TDO Float Delay)
4. Tv = T37 (TDI, TMS Setup Time)
5. Tw = T38 (TDI, TMS Hold Time)
6. Tx = T39 (TDO Valid Delay)
7. Ty = T41 (All Non-Test Outputs Valid Delay)
8. Tz = T42 (All Non-Test Outputs Float Delay)
Figure 16. Test Reset Timings
0.75V
TRST#
T
q
D0009-01
NOTE: Tq=T36 (TRST# Pulse Width)
Datasheet
45