Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 17. Quick Start/Deep Sleep Timing (BCLK Stopping Method)
Normal
Quick Start
Deep Sleep
Stopped
Normal
Quick Start
BCLK
Tv
STPCLK#
Ty
Tx
CPU bus
DPSLP#
stpgnt
Tz
Tw
Changing
Compatibility
Signals
Frozen
V00102-00
NOTES:
1. Tv = T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)
2. Tw = T46 (Setup Time to Input Signal Hold Requirement)
3. Tx = T47 (Deep Sleep PLL Lock Latency)
4. Ty = T48 (PLL lock to STPCLK# Hold Time)
5. Tz = T49 (Input Signal Hold Time)
Figure 18. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)
Normal
Quick Start
Deep Sleep
Normal
Quick Start
BCLK
Tv
STPCLK#
Ty
Tx
CPU bus
DPSLP#
stpgnt
Tz
Tw
Changing
Compatibility
Signals
Frozen
V00103-00
NOTES:
1. Tv = T45 (Stop Grant Acknowledge Bus Cycle Completion to DPSLP# assertion)
2. Tw = T46 (Setup Time to Input Signal Hold Requirement)
3. Tx = T47 (Deep Sleep PLL Lock Latency)
4. Ty = T48 (PLL lock to STPCLK# Hold Time)
5. Tz = T49 (Input Signal Hold Time)
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Datasheet
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