Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 29. Quick Start/Deep Sleep AC Specifications
Symbol
Parameter
Min Max
Unit
Figure
Notes1
Quick Start Cycle Completion to Clock Stop or
DPSLP# assertion
T45
100
BCLKs
15, 16
Quick Start Cycle Completion to Input Signals
Stable
T46
0
µs
15, 16
T47
T48
Deep Sleep PLL Lock Latency
0
0
30
µs
ns
15, 16
15, 16
2
STPCLK# Hold Time from PLL Lock
Input Signal Hold Time from STPCLK#
Deassertion
T49
8
BCLKs
15, 16
NOTES:
1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2. The BCLK, BCLK# Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform
T
h
T
r
VH
VTRIP
CLK
VL
T
f
T
l
T
p
D0003-01
Figure 7. Differential BCLK/BCLK# Waveform (Common Mode)
V2,V3 (max)
BCLK#
Vcross
BCLK
V1,V3 (min)
Datasheet
39
INTEL [ INTEL ]
