Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 25. CMOS and Open-drain Signal Groups AC Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes1, 2
1.5V Input Pulse Width, except
PWRGOOD and LINT[1:0]
Active and
inactive states
T14
2
BCLKs
7
T14B
T15
LINT[1:0] Input Pulse Width
6
2
BCLKs
µs
7
3
PWRGOOD Inactive Pulse Width
10
4, 5
NOTES:
1. All AC timings for CMOS and Open-drain signals are referenced to the crossing point of the BCLK rising
edge and BCLK# falling edge for Differential Clocking and to the rising edge of BCLK at 1.25 V for Single
Ended Clocking. All CMOS and Open-drain signals are referenced at 1.0 V.
2. Minimum output pulse width on CMOS outputs is 2 BCLKs.
3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an
edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4. When driven inactive, or after VCC, VCCT and BCLK, BCLK# become stable. PWRGOOD must remain
below VIL18,MAX until all the voltage planes meet the voltage tolerance specifications in Tables 15 through
18. and BCLK, BCLK# have met the BCLK, BCLK# AC specifications in Tables 30 and 31 for at least 2 µs.
PWRGOOD must rise error-free and monotonically to 1.8 V.
5. If the BCLK Settling Time specification (T60) may be ensured at power-on reset then the PWRGOOD
Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.
PWRGOOD must still remain below V
specifications.
until all the voltage planes meet the voltage tolerance
IL25,max
Table 26. Reset Configuration AC Specifications and Power On/Power Down Timings
(Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
Reset Configuration Signals
(A[15:5]#, BREQ0#, FLUSH#, INIT#,
PICD0) Setup Time
Before
deassertion of
RESET#
T16
4
BCLKs
9
Reset Configuration Signals
(A[15:5]#, BREQ0#, FLUSH#, INIT#,
PICD0) Hold Time
After clock that
deasserts
RESET#
T17
T18
2
20
BCLKs
ms
9
Before
RESET#/PWRGOOD Setup Time
1
1
10
deassertion of
RESET# †
T18A
T18B
VCCT to VTTPWRGD Setup Time
VCC to PWRGOOD Setup Time
ms
ms
10
10
10
BSEL, VID valid time before
VTTPWRGD
T18C
1
µs
10
assertion
T18D
T18E
RESET# inactive to Valid Outputs
RESET# inactive to Drive Signals
1
4
BCLK
9
9
BCLKs
VCC (nominal) is
the VID voltage
setting
Time from VCC (nominal)-12% to
PWRGOOD low
T19A
0
ns
11
All outputs valid after PWRGOOD
low
T19B
T19C
0
0
ns
ns
11
11
All inputs required valid after
PWRGOOD low
†
At least 1 ms must pass after PWRGOOD rises above V
specification until RESET# may be deasserted.
and BCLK, BCLK# meet their AC timing
IH18min
36
Datasheet
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