Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 20. AGTL Bus DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCCT
VREF
Bus Termination Voltage
Input Reference Voltage
Bus Termination Strength
1.25
2/3VCCT
56
V
V
1
2/3VCCT – 2%
50
2/3VCCT + 2%
65
±2%, 2
RTT
W
On-die RTT, 3
NOTES:
1. Refer to Table 14 for minimum and maximum values.
2. V should be created from V by a voltage divider.
REF
CCT
3. The RESET# signal does not have an on-die RTT. It requires an off-die 56.2 Ω ±1% terminating resistor connected to V
.
CCT
Table 21. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
(Sheet 1 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
Input Low Voltage, 1.5 V
CMOS
VIL15
–0.15
VCMOSREFmin – 300 mV
V
Input Low Voltage, 1.8 V
CMOS
VIL18
VIH15
VIH15PICD
VIH18
–0.36
0.36
2.0
V
V
V
V
1, 2
10
Input High Voltage, 1.5 V
CMOS
VCMOSREFmax + 250 mV
VCMOSREFmax + 200 mV
1.44
Input High Voltage, 1.5 V
PICD[1:0]
2.0
11
Input High Voltage, 1.8 V
CMOS
2.0
1, 2
All outputs
are
Open-drain
Output High Voltage, 1.5 V
CMOS
VOH15
N/A
2.0
1.615
V
Output High Voltage, 3.3 V
signals
VOH33
VOL33
3.465
0.8
V
V
3.3V + 5%
Output Low Voltage, 3.3 V
signals
VOL
VCMOSREF
VCLKREF
NOTES:
Output Low Voltage
CMOSREF Voltage
CLKREF Voltage
0.3
1.10
1.312
V
V
V
8
4
9
0.90
1.187
1. Parameter applies to the PWRGOOD signal only.
2. VIlx,min and VIhx,max only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the low state.
See Tables 28 and 29 for DC levels when BCLK and BCLK# are stopped.
3. Measured at 9 mA.
4. VCMOSREF should be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply to maintain
noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that drive these signals.
5. (0 ≤ VIN/OUT ≤ VIhx,max).
6. Specified as the minimum amount of current that the output buffer must be able to sink. However, VOL,max cannot be ensured
if this specification is exceeded.
7. Parameter applies to VTTPWRGD signal only.
8. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
9. ±5% DC tolerance. CLKREF must be generated from the 2.5-V supply used to generate the BCLK signal. AC Tolerance must
be less than –40 dB @ 1 MHz.
10.Applies to all TAP and CMOS signals (not to APIC signals).
11.Applies to PICD[1:0].
Datasheet
33
INTEL [ INTEL ]
