Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.1.5.2
CMOS and Open-drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt state these signals are allowed to toggle. These input
buffers have no internal pull-up or pull-down resistors and system logic may use CMOS or
Open-drain drivers to drive them.
The Open-drain output signals have open drain drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and
pulled-up) when the processor is functioning normally. The FERR# output may be either tri-stated
or driven to V when the processor is in a low-power state depending on the condition of the
SS
floating-point unit. Since this signal is a DC current path when it is driven to V , Intel
SS
recommends that the software clears or masks any floating-point error condition before putting the
processor into the Deep Sleep state.
3.1.5.3
Other Signals
The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states except the
Deep Sleep state. The APIC clock (PICCLK) must be driven whenever BCLK and BCLK# are
driven. Otherwise, it is permitted to turn off PICCLK by holding it at V . BCLK and BCLK#
SS
should be obey the DC levels in Table 33.
In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus
messages. These signals are required to be tri-stated and pulled-up when the processor is in the
Quick Start or Deep Sleep states.
3.2
Power Supply Requirements
3.2.1
Decoupling Guidelines
The ULV Intel® Celeron® processor in Micro FC-BGA package has eight 0805IDC, 0.68-µF
surface mount decoupling capacitors. Six capacitors are on the V supply and two capacitors are
CC
on V
In addition to the package capacitors, sufficient board level capacitors are also necessary
CCT.
for power supply decoupling. The guidelines are as follows:
• High and Mid Frequency V decoupling – Place twenty-four 0.22-µF 0603 capacitors
CC
directly under the package on the solder side of the motherboard using at least two vias per
capacitor node. Ten 10-µF X7 6.3V 1206-size ceramic capacitors should be placed around the
package periphery near the balls. Trace lengths to the vias should be designed to minimize
inductance. Avoid bending traces to minimize ESL.
• High and Mid Frequency V
decoupling – Place ten 1-µF X7R 0603 ceramic capacitors
close to the package. Via and trace guidelines are the same as above.
CCT
• Bulk V decoupling – Minimum of 1200-µF capacitance with Equivalent Series Resistance
CC
(ESR) less than or equal to 3.5 mΩ.
• Bulk V
decoupling – Platform dependent but recommendation is minimum of 660-µF with
ESR less than or equal to 7 mΩ.
CCT
Refer to the appropriate platform design guidelines for bulk decoupling recommendations.
22
Datasheet
INTEL [ INTEL ]
