Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.1.2
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage
levels supported by the TAP interface, Intel recommends that the ULV Intel® Celeron® processor
and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain after any
devices with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer should be used
to reduce the TDO output voltage of the last 3.3/5.0 V device down to the 1.5-V range that the ULV
Intel Celeron processor may tolerate. Multiple copies of TMS and TRST# must be provided, one
for each voltage level.
A Debug Port and connector may be placed at the start and end of the JTAG chain containing the
processor, with TDI to the first component coming from the Debug Port and TDO from the last
component going to the Debug Port. There are no requirements for placing the ULV Intel Celeron
processor in the JTAG chain, except for those that are dictated by voltage requirements of the TAP
signals.
3.1.3
3.1.4
Catastrophic Thermal Protection
The ULV Intel Celeron processor does not support catastrophic thermal protection or the
THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the
system against excessive temperatures. If the external thermal sensor detects a processor junction
temperature of 101° C (maximum), both the V and V
supplies to the processor must be
CC
CCT
reduced to at least 50% of the nominal values within 500 ms and are recommended to be turned off
completely within 1 second to prevent damage to the processor. processor temperature must be
monitored in all states including low power states.
Unused Signals
All signals named NC must be unconnected. Unused AGTL inputs, outputs, and bidirectional
signals should be unconnected. Unused CMOS active low inputs should be connected to 1.5 V and
unused active high inputs should be connected to V . Unused Open-drain outputs should be
SS
unconnected. When tying any signal to power or ground, a resistor will allow for system testability.
For unused signals, Intel suggests that 1.5-kΩ resistors are used for pull-ups and 1.0-kΩ resistors
are used for pull-downs.
PICCLK must be driven with a clock that meets specification and the PICD[1:0] signals must be
pulled up separately to 1.5 V with 150-Ω resistors, even if the local APIC is not used.
If the TAP signals are not used then the inputs should be pulled to ground with 1-kΩ resistors and
TDO should be left unconnected.
3.1.5
Signal State in Low-power States
System Bus Signals
3.1.5.1
All of the system bus signals have AGTL input, output, or input/output drivers. Except when
servicing snoops, the system bus signals are tri-stated and pulled up by the termination resistors.
Snoops are not permitted in the Deep Sleep state.
Datasheet
21
INTEL [ INTEL ]
