Electrical Specifications
Figure 15. Source Synchronous 4X Timings
T0
T1
T2
2.5 ns 5.0 ns 7.5 ns
BCLK1
BCLK0
DSTBp# (@ driver)
DSTBn# (@ driver)
TH
TD
TA TB TA
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
TC
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe
TB = T22: Source Sync. Data Output Valid Delay After Data Strobe
TC = T27: Source Sync. Setup Time to BCLK
TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
TE = T25: Source Sync. Input Setup Time
TG = T26: Source Sync. Input Hold Time
TH = T29: First Data Strobe to Subsequent Strobes
TJ = T20: Source Sync. Data Output Valid Delay
Mobile Intel Pentium 4 Processor-M Datasheet
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INTEL [ INTEL ]
