Electrical Specifications
Figure 23. Stop Grant/Sleep/Deep Sleep Timing
Stop
Grant
Stop
Grant
Normal
Sleep
Deep Sleep
Sleep
Normal
BCLK[1:0]
DPSLP#
Tv
STPCLK#
Ty
CPU bus
SLP#
stpgnt
Tw
Tx
Tt
Tu
Changing
Tz
Compatibility
Signals
Changing
Frozen
V0011-02
Tt = T70 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
Tu = T71 (Input Signals Stable to SLP# assertion requirement)
Tv = T72 (SLP# to DPSLP# assertion)
Tw = T73 (Deep Sleep PLL lock latency)
Tx = T74 (SLP# Hold Time)
Ty = T75 (STPCLK# Hold Time)
Tz = T76 (Input Signal Hold Time)
Mobile Intel Pentium 4 Processor-M Datasheet
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INTEL [ INTEL ]
