Electrical Specifications
Figure 16. Power Up Sequence
BCLK
Vcc
PWRGOOD
RESET#
VCCVID
Tc
Td
Ta
Tb
VID_GOOD
VID[4:0],
BSEL[1:0]
Ta= 1us minimum (VCCVID > 1V to VID_GOOD high)
Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time)
Tc= T37 (PWRGOOD inactive pulse width)
Td= T36 (PWRGOOD to RESET# de-assertion time)
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon. For more
information on implementation refer to the Intel Mobile Northwood
Processor and Intel 845MP Platform RDDP.
Figure 17. Power Down Sequence
Vcc
PWRGOOD
VCCVID
VID_GOOD
VID[4:0]
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon. For more
information on implementation refer to the Intel Mobile Northwood
Processor and Intel 845MP Platform RDDP.
1. This timing diagram is not intended to show specific times. Instead a
general ordering of events with respect to time should be observed.
2. When VCCVID is less than 1V, VID_GOOD must be low.
3. Vcc must be disabled before VID[4:0] becomes invalid.
4. VCCVID and Vcc regulator can be disabled simultaneously
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Mobile Intel Pentium 4 Processor-M Datasheet
INTEL [ INTEL ]
