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249033-001 参数 Datasheet PDF下载

249033-001图片预览
型号: 249033-001
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的T1 LH / SH收发器,用于DS1 / DSX - 1或PRI应用 [Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications]
分类和应用:
文件页数/大小: 48 页 / 789 K
品牌: INTEL [ INTEL ]
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LXT362 Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications  
2.3  
Receiver  
A 1:1 transformer provides the interface to the twisted-pair line (RTIP/RING). Recovered data is  
output at RPOS/RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK.  
Refer to Table 27 on page 41 for receiver timing specifications.  
2.3.1  
Receive Equalizer  
The receive equalizer processes the signal received at RTIP and RRING. The equalizer gain is up  
36 dB. As shown in Table 10, Equalizer Control inputs (EC1 through EC4) determine the  
maximum gain applied to the equalizer. In Host mode, EC1 through 4 are established by bits 0  
through 3 of Control Register #1 (CR1), respectively. In Hardware mode, pins EC1, EC2, EC3, and  
EC4 specify equalizer gain setting. With EC1 Low, up to 36 dB of gain may be applied. When EC1  
is High, 26 dB is the gain limit to provide an increased noise margin in shorter loop operations.  
2.3.2  
Receive Data Recovery  
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The  
peak detector samples the inputs and determines the maximum value of the received signal. The  
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.  
After processing through the data slicers, the received signal goes to the data and timing recovery  
section, then to the B8ZS decoder (if selected) and to the receive monitor. The data and timing  
recovery circuits provide input jitter tolerance significantly better than required by AT&T  
Pub 62411. See Test Specificationson page 38 for details.  
2.3.3  
2.3.4  
Receive Digital Data Interface  
Recovered data is routed to the Loss of Signal (LOS) Monitor. In Host mode, it also goes through  
the Alarm Indication Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled  
or disabled in the receive data path or the transmit path. Received data can be routed to the B8ZS  
decoder or bypassed. Finally, the device may send the digital data to the framer as either unipolar  
or bipolar data.  
Receiver Monitor Mode  
The receive equalizer can be used in Monitor mode applications. Monitor mode applications  
require 20 dB to 30 dB resistive attenuation of the signal, plus a small amount of cable attenuation  
(less than 6 dB). In Host mode, setting bit CR3.EQZMON = 1 configures the device to operate in  
Monitor mode. Note that the LXT362 must be in long-haul receiver mode (set bits  
CR1.EC4:1 = 0xx0, 1001, or 1010) to enable Monitor mode. Note that the Monitor mode feature is  
not available in Hardware mode.  
2.4  
Jitter Attenuation  
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides the jitter attenuation function.  
The JAL requires no special circuitry, such as an external quartz crystal or high-frequency clock  
(higher than the line rate). Rather, its timing reference is MCLK.  
16  
Datasheet  
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