M10-DATASHEET
2015.05.04
51
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
Typ
Max
Min
Max
Min
Max
tLOCK
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
—
—
1
—
1
—
1
ms
configuration
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Single Supply Devices LVDS Receiver Timing Specifications
Table 43: LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices—Preliminary
LVDS receivers are supported at all banks.
–C7, –I7
–A7
–C8
Symbol
Parameter
Mode
Unit
Min
5
Max
145
145
145
145
145
290
Min
5
Max
100
100
100
100
100
200
Min
Max
100
100
100
100
100
200
×10
×8
×7
×4
×2
×1
5
5
5
5
5
5
MHz
MHz
MHz
MHz
MHz
MHz
5
5
Input clock frequency
(high-speed I/O
5
5
fHSCLK
5
5
performance pin)
5
5
5
5
MAX 10 FPGA Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
