M10-DATASHEET
2015.05.04
55
Memory Output Clock Jitter Specifications
–C8
–I6, –C7, –I7
–A7
Symbol
Parameter
Mode
Unit
Min
Max
Min
Max
Min
Max
tLOCK
Time required for the
PLL to lock, after CONF_
DONE signal goes high,
indicating the
—
—
1
—
1
—
1
ms
completion of device
configuration
Memory Output Clock Jitter Specifications
MAX 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for MAX 10 devices calibrate automatically.
The memory output clock jitter measurements are for 200 consecutive clock cycles.
The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a PHY clock
network.
DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.
Table 45: Memory Output Clock Jitter Specifications for MAX 10 Devices—Preliminary
–6 Speed Grade
–7 Speed Grade
Parameter
Symbol
Unit
Min
Max
100
200
Min
Max
125
250
Clock period jitter
tJIT(per)
tJIT(cc)
–100
—
–125
—
ps
ps
Cycle-to-cycle period jitter
Related Information
Literature: External Memory Interfaces
Provides more information about external memory system performance specifications, board design guidelines, timing analysis, simulation, and
debugging information.
Configuration Specifications
This section provides configuration specifications and timing for MAX 10 devices.
MAX 10 FPGA Device Datasheet
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