M10-DATASHEET
2015.05.04
48
Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications
–C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
100
80
Typ
—
—
—
—
—
—
—
Max
200
200
200
200
200
200
55
Min
100
80
Max
200
200
200
200
200
200
55
Min
100
80
Max
200
200
200
200
200
200
55
×10
×8
×7
×4
×2
×1
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
—
—
Data rate (low-
70
70
—
70
—
HSIODR speed I/O
40
40
—
40
—
performance pin)
20
20
—
20
—
10
10
—
10
—
tDUTY
Duty cycle on
transmitter output
clock
45
45
—
45
—
TCCS(64) Transmitter
—
—
—
410
—
—
410
—
—
410
ps
channel-to-channel
skew
(65)
tx Jitter
tRISE
Output jitter
Rise time
—
—
—
—
1,000
—
—
—
—
1,000
—
—
—
—
1,000
—
ps
ps
20 – 80%,
500
500
500
CLOAD = 5 pF
tFALL
Fall time
20 – 80%,
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
CLOAD = 5 pF
tLOCK
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
ms
configuration
(64)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
(65)
MAX 10 FPGA Device Datasheet
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