M10-DATASHEET
2015.05.04
53
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
–C7, –I7
–A7
–C8
Symbol
Parameter
Mode
Unit
Min
—
Max
Min
—
Max
1,000
1
Min
—
Max
1,000
1
(68)
tx Jitter
tLOCK
Input jitter
—
—
1,000
1
ps
Time required for the
PLL to lock, after CONF_
DONE signal goes high,
indicating the
—
—
—
ms
completion of device
configuration
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Table 44: LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for MAX 10 Dual Supply Devices—Preliminary
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS receivers are supported at all banks.
–I6, –C7, –I7
–A7
–C8
Symbol
Parameter
Mode
Unit
Min
Max
360
360
360
360
360
360
Min
5
Max
320
320
320
320
320
320
Min
5
Max
320
320
320
320
320
320
×10
×8
×7
×4
×2
×1
5
5
5
5
5
5
MHz
MHz
MHz
MHz
MHz
MHz
5
5
Input clock frequency
(high-speed I/O
5
5
fHSCLK
5
5
performance pin)
5
5
5
5
(68)
TX jitter is the jitter induced from core noise and I/O switching noise.
MAX 10 FPGA Device Datasheet
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