M10-DATASHEET
2015.05.04
47
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications
Table 41: Emulated LVDS_E_3R Transmitter Timing Specifications for MAX 10 Single Supply Devices—Preliminary
Emulated LVDS_E_3R transmitters are supported at the output pin of all I/O banks.
–C7, –I7
Typ
—
–A7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–C8
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Symbol
Parameter
Mode
Unit
Min
5
Max
142.5
142.5
142.5
142.5
142.5
285
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
100
100
100
100
100
200
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
100
100
100
100
100
200
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
5
—
5
5
Input clock
5
—
5
5
frequency (high-
speed I/O
fHSCLK
5
—
5
5
performance pin)
5
—
5
5
5
—
5
5
100
80
70
40
20
10
5
—
285
100
80
70
40
20
10
5
100
80
70
40
20
10
5
—
285
Data rate (high-
—
285
HSIODR speed I/O
—
285
performance pin)
—
285
—
285
—
100
5
—
100
5
5
Input clock
5
—
100
5
5
frequency (low-
speed I/O
fHSCLK
5
—
100
5
5
performance pin)
5
—
100
5
5
5
—
200
5
5
MAX 10 FPGA Device Datasheet
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