M10-DATASHEET
2015.05.04
54
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
–I6, –C7, –I7
–A7
–C8
Symbol
Parameter
Mode
Unit
Min
100
80
70
40
20
10
5
Max
720
720
720
720
720
360
150
150
150
150
150
300
300
300
300
300
300
300
400
500
Min
100
80
70
40
20
10
5
Max
640
640
640
640
640
320
150
150
150
150
150
300
300
300
300
300
300
300
400
500
Min
100
80
70
40
20
10
5
Max
640
640
640
640
640
320
150
150
150
150
150
300
300
300
300
300
300
300
400
500
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
Data rate (high-speed I/
O performance pin)
HSIODR
5
5
5
Input clock frequency
(low-speed I/O
5
5
5
fHSCLK
5
5
5
performance pin)
5
5
5
5
5
5
100
80
70
40
20
10
—
—
100
80
70
40
20
10
—
—
100
80
70
40
20
10
—
—
Data rate (low-speed I/
O performance pin)
HSIODR
SW
Sampling window
Input jitter
(69)
tx Jitter
—
ps
(69)
TX jitter is the jitter induced from core noise and I/O switching noise.
MAX 10 FPGA Device Datasheet
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