M10-DATASHEET
2015.05.04
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Dual Supply Devices True LVDS Transmitter Timing Specifications
Dual Supply Devices True LVDS Transmitter Timing Specifications
Table 40: True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary
True LVDS transmitter is only supported at the bottom I/O banks.
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
Typ
Max
Min
Max
Min
Max
×10
5
—
360 (60)
,
5
310
5
300
MHz
335 (61)
360
×8
×7
5
5
—
—
5
5
—
—
320
310
5
5
—
—
320
300
MHz
MHz
360 (60)
,
Input clock
frequency
335 (61)
fHSCLK
×4
×2
5
5
—
—
—
—
360
360
360
5
5
—
—
—
—
320
320
320
620
5
5
—
—
—
—
320
320
320
600
MHz
MHz
MHz
Mbps
×1
5
5
5
×10
100
720 (60)
,
100
100
670 (61)
×8
×7
80
70
—
—
720
80
70
—
—
640
620
80
70
—
—
640
600
Mbps
Mbps
720 (60)
,
670 (61)
HSIODR
Data rate
×4
×2
×1
—
40
20
10
45
—
—
—
—
720
720
360
55
40
20
10
45
—
—
—
—
640
640
320
55
40
20
10
45
—
—
—
—
640
640
320
55
Mbps
Mbps
Mbps
%
tDUTY
Duty cycle on
transmitter output
clock
(60)
(61)
Applicable to –I6 speed grade.
Applicable to –C7 and –I7 speed grades.
MAX 10 FPGA Device Datasheet
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