M10-DATASHEET
2015.05.04
46
Dual Supply Devices True LVDS Transmitter Timing Specifications
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
Typ
Max
Min
Max
Min
Max
TCCS(62)
Transmitter
—
—
—
410
—
410
—
410
ps
channel-to-
channel skew
(63)
tx Jitter
Output jitter
Rise time
—
—
—
—
380
—
—
—
—
380
—
—
—
—
380
—
ps
ps
tRISE
20 – 80%, CLOAD
= 5 pF
500
500
500
tFALL
tLOCK
Fall time
20 – 80%, CLOAD
= 5 pF
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
ms
configuration
(62)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
(63)
MAX 10 FPGA Device Datasheet
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