M10-DATASHEET
2015.05.04
44
Single Supply Devices True LVDS Transmitter Timing Specifications
–C7, –I7
Typ
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
—
Max
1,000
—
Min
—
Max
1,000
—
Min
—
Max
1,000
—
(59)
tx Jitter
Output jitter
Rise time
—
—
ps
ps
tRISE
20 – 80%, CLOAD
= 5 pF
—
500
—
500
—
500
tFALL
tLOCK
Fall time
20 – 80%, CLOAD
= 5 pF
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
ms
configuration
(59)
TX jitter is the jitter induced from core noise and I/O switching noise.
MAX 10 FPGA Device Datasheet
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