IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
5.1.39 T2INTCON (03ah), T1INTCON (038h), and T0INTCON (032h) (Slave Mode)
Timer INTerrupt CONtrol Register. The three timers, Timer 2, Timer 1, and Timer 0, each have
an interrupt control register, whereas in master mode all three are masked and prioritized in one
register (TCUCON). The value of these registers is 000Fh at reset (see Table 61).
Table 61. Timer Interrupt Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
MSK PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the timer interrupts in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.40 DMA1CON (036h) and DMA0CON (034h) (Master Mode)
DMA CONtrol Register. The DMA0 and DMA1 interrupts have interrupt type 0ah and 0bh,
respectively. The value of these registers is 000Fh at reset (see Table 62).
Table 62. DMA Interrupt Control Register (Master Mode)
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
MSK PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the DMA interrupts in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.41 DMA1CON (036h) and DMA0CON (034h) (Slave Mode)
DMA CONtrol Register. The two DMA control registers maintain their original functions and
addressing that they possessed in Master Mode. The value of these registers is 000Fh at reset
(see Table 63).
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